Investors

The merchant PPCU thesis, honestly staged.

EP is becoming the default in-space drivetrain; the PPU is its acknowledged bottleneck; the merchant supply is nine vendors, one outside the US/EU, none in India — and this team has built the hardware once already, inside ISRO.

The worldwide landscape, in depth →

Stage today
TRL 4core ZVZCS discharge stage — silicon breadboard operational (lightweight GaN EM in design)
Pre-seedbootstrapped; no external capital to date
Pre-revenueon the PPCU line; entity has small services history
3founders — power topology · converters · high-rel control
What the raise unlocks

Breadboard → thruster-coupled engineering model, 18 months

M 1–6

Freeze Class-II architecture

Lightweight GaN-based EM design informed by the bench-proven silicon stage; radiation-data-backed GaN parts selection and derating; Bengaluru lab; first two engineering hires.

M 7–12

EM through defined gates

Vacuum load test · thermal-vac soak · EMI pre-scan · arc-survival and ignition-transient campaigns against a thruster simulator.

M 13–18

Coupled firing & first orders

Thruster-coupled vacuum test with a partner thruster; IN-SPACe authorization; first LOI-to-order conversions. Exit at TRL 5–6.

~55%engineering team
~25%lab & test campaigns
~12%qualification & compliance
~8%go-to-market
Defensibility, stated plainly

Know-how first, filings to follow

No patents yet — the moat today is scarce, flight-programme-acquired design know-how: soft-switching a space-grade high-voltage stage through ignition and arcing without losing the EMI budget, now being carried into wide-bandgap GaN. Filings are planned where they protect rather than disclose; qualification evidence and customer integration depth are the compounding defenses in this market.

Market map (23 : 9 : 1 : 0), source table and heritage documentation are available in diligence. A bench demonstration of the running breadboard is available under NDA.

The deck (PDF) Deck on the web Start diligence